1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
2. Description of the Related Art
In order to use a word line as a metal in a three-dimensional flash device, after a channel plug is formed as in Terabit Cell Array Transistors (TCAT), a sacrificial layer is stripped and an oxide/nitride/oxide (ONO) layer and a metal are deposited thereon. Thereafter, a word line is formed through an isolation process.
FIG. 1A is a perspective view of a conventional nonvolatile memory device. FIG. 1B is a layout view of FIG. 1A.
Referring to FIGS. 1A and 1B, a plurality of channel plugs 11 is formed on a substrate (not illustrated). Each of the channel plugs 11 pierces a word line 12. A plurality of word lines 12 are stacked in a plurality of layers. Both ends of the word lines 12 are trimmed in a trimmed region 13 to have a stepwise configuration. The word lines 12 have a stepwise configuration in which the uppermost word line 12 is shortest and the lowermost word line 12 is longest. That is, the word lines 12 are stacked and form rows extending across a cell region 100. However, once outside the cell region 100, the word lines 12 are trimmed to form the stepwise configuration, and the ends of the word lines 12 are connected to word line contacts 14.
Thus, the trimmed region 13 is a region in which the word line contacts 14 are connected. The trimmed region 13 generally has a width of approximately 500 nm.
The conventional technology of FIGS. 1A and 1B alternately stacks dielectric layers and sacrificial layers several times, selectively removes the sacrificial layers, and forms the word lines 12 in the portions cleared of the sacrificial layers. For example, in a 128-giga class flash memory, dielectric layers and sacrificial layers are stacked in 16 layers. For example, the dielectric layers may be formed using oxide, and the sacrificial layers may be formed using nitride. In this structure, in the case of the lowermost word line 12, an approximately 9000 nm (=16×500 nm) empty space from a trimming start region 101 to a trimming end region 102 must be supported by a dielectric layer (e.g., an oxide layer).
However, there is a high probability that the trimming region collapses due to a thermal stress in the sacrificial layer (nitride layer) stripping process and the subsequent ONO process. Consequently, the word lines 12 are not properly formed, thus making it difficult to form the device.